Reference no: EM13974743

A Computer has a cache with block size 64 bytes the main memory has k banks, each bank being c bytes wide consecutive c-byte chunks are mapped on consecutive banks with warp-around all the k banks can be accessed in parallel, but two accesses to the same bank must be serialized A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks parallel each iteration requires decoding the bank numbers to be accessed in parallel and this takes k/2 ns the latency of one bank access is 80 ns if c=2 and k=24 then what is main memory of latency of retrieving a cache block starting at address zero.