A 2.5 ghz pipelined mips processor

Reference no: EM13159783

While working with a 2.5 GHz pipelined MIPS processor which has a L2 cache unit miss penalty of 10 ns and a memory miss penalty of 50 ns, determine the Effective CPI for a program with a 0.4% instruction miss rate, 11.4% data miss rate, a L2 miss rate of 0.5% and 18% of instructions are either load or store instruction. How many times faster is the processor when cache operations are not considered?

Reference no: EM13159783

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