Reference no: EM13380404

1. Consider the following code fragment for the MIPS five stage pipelined processor:

instruction1 add $1, $8, $3 //$1 = $8 + $3

instruction2 sub $2, $1, $8 //$2 = $1 - $8

instruction3 add $3, $2, $1 //$3 = $2 + $1

instruction4 sub $5, $1, $2 //$5 = $1 - $2

instruction5 add $4, $2, $1 //$4 = $2 + $1

instruction6 add $9, $12, $11 //$9 = $12 + $11

a) You are to identify the problems, if any, which may be encountered in the pipeline. If you do identify any problems you are to explain them by using the instruction format terms <rd>, <rs>, <rt> for those instructions where there are problems.

b) At the end of clock cycle 6, which registers are being read and which register is being written. You must also identify which registers belong to which instruction in your answer.

b) Explain what the forwarding unit is doing during clock cycle 6. You are to identify which, if any, comparisons are being made in the instruction format terms <rd>, <rs>, <rt> for those instructions where there might be comparisons.

d) The code fragment is now changed to:

instruction1 add $1, $2, $3 //$1 = $2 + $3

instruction2 sub $4, $1, $6 //$4 = $1 - $6

instruction3 add $3, $2, $1 //$3 = $2 + $1

instruction4 lw $6, 8($3) //$6 = Memory[$3 + 8]

instruction5 sub $5, $1, $6 //$5 = $1 - $6

instruction6 add $9, $12, $11 //$9 = $12 + $11

Explain what the hazard detection unit is doing, for this new code fragment, during clock cycle 6 of execution. You are to state any comparisons that are being made in the instruction format terms <rd>, <rs>, <rt> for those instructions that might be compared. You are to state what the hazard unit will do in this case.

2. The following diagram reproduces the MIPS Single Cycle Datapath (Figure 5.1) from Computer Organization & Design: The Hardware Software Interface by Patterson and Hennessy.

a) In this representation every instruction takes at most 4 steps to complete a clock cycle. Explain what happens in each step of the clock cycle.

b) Clock cycle time = delay through combinational logic + register setup time + clock skew + delay through register. Briefly explain:

i) Why there is a delay through combinational logic.

ii) What the register setup time is.

iii) What clock skew is.

iv) What the delay through register is.

c) What type of MIPS instruction is represented by the diagram below? Provide two examples of this type of MIPS instruction.

d) Explain what each field represents in the diagram from part c of this question (except the shamt field). In your explanation include the number of bits that each field requires and show each field's bit representation in the instruction format.

3)

a) Given the following MIPS machine instructions:

(i) 00010010111110010111111010111001

(ii) 00000000110010010111100000101010

For each machine instruction:

a) What is the instruction format class and why?

b) What operation will be performed and how did you identify the operation?

c) In decimal and in instruction format order, what registers (if any) represent rd, rs, rt? Hint rd is not always used. If you think no registers are used, state it.

d) What MIPS registers, if any, are used? In the case that MIPS registers are used, name them instruction format order and in terms of $at, $v0, $t0 etc. Hint rd is not always used. If you think no registers are used, state so.

e) In the case that an immediate value or an address is used, express it in hex. If you think the instruction does not use an immediate or an address, state so.

b) Explain the operation of the 'MIPS andi ' instruction. Illustrate your answer with an appropriate example. In your answer you must provide details of the andi instruction format and of what each field in that instruction format does and how an andi instruction is identified.

4)

Explain the operation of the following MIPS assembler instruction as it passes through each stage of the MIPS pipeline. You are to highlight any parallelism and redundancy that may occur as the instruction passes through the various pipeline stages. You are to assume there is no impact on this instruction by previously executed instructions. A diagram is not required.