Working of DSP Processor

Most DSP processors share some common basic features designed to support high-performance, repetitive, numerically intensive tasks. The often cited of the features is ability to perform one or more multiply-accumulate operations (often called "MACs") in a single instruction cycle. The multiply accumulate operation is used in DSP algorithms which involve computing a vector dot product, such  as digital filters, correlation, and Fourier transforms. To achieve single cycle MAC, processors of DSP integrates multiply-accumulate hardware into the main data path of the processor, as shown in Figure 1. Some of the recent DSP processors provide 2 or more multiply-accumulate units, by allowing the multiply accumulate operations to be performed in parallel. In addition, to allow a series of multiply-accumulate operations to proceed without the possibility of arithmetic overflow (the generation of numbers greater than the maximum value the processor's accumulator can hold), DSP processors generally provide extra "guard" bits in the accumulator. For example, the Motorola DSP processor family examined in Figure 1 offers eight guard bits  A second feature shared by DSP processors is the ability to complete several accesses to  memory in a single instruction cycle. This allows the processor to take an instruction while simultaneously fetching operands and/or storing the result of a previous instruction to memory. For instance, in calculating the vector dot product for an FIR filter, most of the DSP processors are able to perform the MAC while simultaneously loading the data sample and coefficient for the next MAC. Such type of single cycle multiple memory accesses are subject to many restrictions often. Typically, all but 1 of the memory locations accessed should reside on-chip, and multiple the memory accesses can take place with the certain instructions.

To support simultaneous access of multiple memory locations, DSP processors give multiple onchip buses, multi-ported on-chip memories, and in multiple independent memory banks.  A 3rd feature used often to speed arithmetic processing on DSP processors is 1 or more dedicated address generation units. As the appropriate addressing registers have been configured, address generation unit operates in background (that is, without using main data path of the processor),

 

forming the addresses  required for the operand accesses in parallel with execution of arithmetic instructions. On the contrary general-purpose processors require extra cycles to generate the addresses required to load operands. DSP processor address generation units support typically a selection of addressing modes modified to DSP applications. The most common out of these is register-indirect addressing with the post-increment, which is used in the situations where a repetitive computation is performed on data sequentially stored in memory.  Modulo addressing is supported often, to simplify the usage of circular buffers. Some processors support  bit-reversed  addressing, which increases speed of certain fast Fourier transform (FFT) algorithms. As many DSP algorithms involve performing repetitive computations, most DSP processors give special support for the efficient looping. Often, a special loop or repeat instruction is provided, which allows the programmer to implement a for the next loop without expending instruction cycles for updating and testing the loop counter or branching back to the top of the loop. Finally, to allow the low-cost, high-performance output and input, most of the DSP processors incorporate 1 or more serial or parallel I/O interfaces, and specialized I/O  handling mechanisms like low-overhead interrupts and direct memory access (DMA) to allow the data transfers to proceed with less or no intervention from the rest of the processor. The increasing popularity of DSP functions like speech coding and audio processing has led the designers to consider implementing DSP on general-utility processors like that of desktop CPUs and microcontrollers. Nearly all the general-utility processor manufacturers have responded by adding the signal processing capabilities to their chips. Examples comprise the MMX and SSE instruction set extensions to Intel Pentium line, and extensive DSP-oriented retrofit of Hitachi's SH-2 microcontroller to form SH-DSP. In some of the cases, system designers can prefer to use the general-purpose processor rather than the DSP processor. However, general-purpose processor architectures require several instructions to perform operations which can be performed with just 1 DSP processor instruction, general-utility processors run at extremely fast clock speeds. If the designer requires performing non- DSP processing, and then using a general-utility processor for DSP and non-DSP processing both could reduce the system parts count and lower costs versus using a distinct DSP processor and general-utility microprocessor. Additionally, some popular general-utility processors feature a tremendous selection of application development tools. On the other hand, as general-purpose utility architectures lack features that simplify

The DSP programming, software development is at times more tedious than on the DSP processors and can result in awkward code which is difficult to maintain. Moreover, if general-utility processors are used for signal processing only, they are hardly cost-effective as compared to DSP chips designed particularly for the task. Therefore, at least in the short run, we believe that the system designers will continue to use traditional the DSP processors for majority of DSP intensive applications. We concentrate on DSP processors in this paper. 

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