Biasing the Field Effect Transistor

Voltage Divider Bias :

The biasing circuit is based on the single power supply is shown in the figure 1. This is like the voltage divider bias used with the bipolar transistor.

Figure 1

The Thevenin voltage V_TH which is applied to the gate is

The Thevenin resistance can be given as

The gate current is supposed to be negligible. V_TH is the DC voltage from gate to ground.

The drain current I_D can be given by

and the dc voltage from the drain to ground is V_D = V_DD - I_D R_D.

If the value of V_TH  is large enough to swamp out V_GS  the drain current is approximately constant for any JFET as shown in the figure 2.

Figure  2

There is a problem in JFET. In a BJT, V_BE  is approximately 0.7V, with only minor variations from one transistor to other. In the FET, V_GS can vary some volts from one JFET to another. It is thus, difficult to make V_TH large enough to swamp out V_GS. For this very reason, the voltage divider bias is less effective with, FET than the BJT. Hence, V_GS is not negligible. The current increases slightly from Q₂ to Q₁. However, voltage divider bias maintains ID nearly constant.

Consider the voltage divider bias circuit as shown in the figure 3.

Difference in I_{D (min)} and I_{D (max)} is less

V_{D (max)} = 30 - 2.13 * 4.7 = 20 V V_{D (min)} = 30 - 2.67 * 4.7 = 17.5 V

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