Clamper Circuits

Positive Clamper:

The positive clamper circuit is shown in the figure 1, which introduces positive DC voltage equal to peak of the input signal. The operation of circuit is same to the negative clamper.

Figure 1          

 Figure 2

Suppose the input signal varis form +10 V to -10 V. During the first negative half cycle as Vi rises from 0 to -10 V, the diode conducts. Assuming an ideal diode, the voltage of it, which is also the output should be zero during the time from 0 to t1. The capacitor charges during the period to 10 V, with polarity shown.

After that V_i begins to drop which means the anode of D is negative relative to cathode, (V_D= v_i - v_C) thus reverse biasing the diode and preventing the capacitor from discharging.  Figure 2. Since the capacitor is holding its charge it behaves like a DC voltage source while diode appears as an open circuit, thus the equivalent circuit becomes an input supply in series with the +10V DC voltage and the resultant output voltage is sum of the instantaneous input voltage and DC voltage (+10 V).

To clamp input signal by a voltage other than the peak value, a DC source is needed. As shown in the figure 3, the DC source reverse biases the diode.

The input voltage swings from +10 V to -10 V. In negative half cycle when the voltage exceed 5V then D conduct. During input voltage variation from -5 V to -10 V, the capacitor charges to 5 V with the polarity shown in the figure 3. After that D becomes reverse biased and open circuited. Then the complete AC signal is shifted upward by 5 V. The output waveform is shown in the figure 4.

Figure 3     

Figure 4

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