Multiply-and-Accumulate

DSP algorithms can be characterized by intensive number crunching which may exceed the capabilities of general purpose CPU. Because of arithmetic instructions tailored specifically to DSP requires a DSP processor can be quite faster for the specific tasks. The most usual special purpose task in the digital signal processing is multiply-and -accumulate (MAC) operation shown by the FIR filter

 

This type of repeated MAC operation take place in other situations as well. Further, the operands b and x are not required to have the same index j. Letting x and b have independent indices k and j, the following loop accomplishes MAC operation

    Loop:

      update j, update k
        

Loop overhead
A general utility CPU would implement the above sum of the products operation in the fixed length loop such that

    For i = 0 to M

      {statements}

which involves considerable overhead apart from statements. This overhead comprises of:

 

The DSP processors provide a zero-overhead hardware mechanism (DO or REPEAT) which can repeat an instruction or a set of the instructions a prescribed number of times. Because of hardware support for the repetition structure no clock cycles are wasted on incrementing or branching and checking the loop index. The number of loop iterations is essentially limited. If the loop nesting is allowed not all the loops may be zero-overhead .

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