Memory Architecture
Load registers x and b simultaneously .As bj and xk are totally independent we can make provision to read them at the same time from memory into the appropriate registers. In the standard CPU situation there is only one bus connection to memory; and even connecting 2 buses to the same (1) memory does not help; and the therefore called as "dual port memories" are expensive and slow. In the radical departure from memory architecture of the standard CPU, the DSP can describe multiple memory banks each of them served by the bus of its own. Now bj and xk can be
loaded at the same time from memory into the registers j and k, given in the sequence below by listing the 2 operations on the same line, the sequence now taking five units of time:
We next turn to last 3 lines (fetch, decode and execute) in sequence.
Caches Standard CPUs uses the instruction caches to accelerate the execution. The process of caching implies different amounts of run-time (unpredictability) depending upon the state of the caches when operation begins. However, DSPs are designed for the real-time use where the prediction of the exact timing can be critical. Thus caches are generally avoided in DSPs as the caching complicates the computation of program execution time.
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