Potential-Divider Biasing:

Fet-potential-divider-biasing

A bit modified form of DC bias is provided by circuit shown in the figure. The resistors R_Gl and R_G2  form the potential divider across drain supply V_DD. The voltage V₂  across R_G2  provides necessary bias. The additional gate resistor R_Gl  from gate to supply voltage facilitates in the larger adjustment of DC bias point and permits use of the larger valued RS.

The gate is reverse biased so that I_G = 0 and gate voltage

V_G =V₂ = (V_DD/R _G1 + R _G2 ) *R_G2

And

V_GS = v_G - v_s = V_G - I_D Rs

The operating point can be determined as

I_D = (V₂ - V_GS)/ R_S

And

V_DS = V_DD - I_D (R_D + R_S)

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