Potential-Divider Biasing:
Fet-potential-divider-biasing
A bit modified form of DC bias is provided by circuit shown in the figure. The resistors RGl and RG2 form the potential divider across drain supply VDD. The voltage V2 across RG2 provides necessary bias. The additional gate resistor RGl from gate to supply voltage facilitates in the larger adjustment of DC bias point and permits use of the larger valued RS.
The gate is reverse biased so that IG = 0 and gate voltage
VG =V2 = (VDD/R G1 + R G2 ) *RG2
And
VGS = vG - vs = VG - ID Rs
The operating point can be determined as
ID = (V2 - VGS)/ RS
And
VDS = VDD - ID (RD + RS)
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