Defination of Harvard architecture 

Now we consider fetching of 1 instruction while the earlier ones are still being executed or decoded. There can now be a clash while fetching the instruction from memory at same time that the data related to the instruction prior is being transferred from or to memory. The solution uses separate memory banks and separate buses. Earlier we used different memory banks for the various categories of data but now hear we are talking about a memory bank for the instructions versus a memory bank for the data. Memory banks have the independent address spaces and are known as program memory and data memory - resulting in Harvard architecture. The CPU can take the next instruction and at the same time do a load/store of a memory word. Standard computers use the same memory space for program and data, this being called as von Neumann architecture.

DSPs abide by the Harvard architecture to be able to overlap the instruction fetches with the data transfers. Idea of overlapping brings us to the pipelining.

[The availability of modern cache system has considerably alleviated the problem of von Neumann bottle neck. The most modern computers labelled "Harvard architecture" allow the access to contents of the instruction memory as though it were data and are known as modified Harvard architecture, used in the niche applications such as DSP and microcontrollers]

  In short, so far the efforts made by us to enhance the DSP processor's speed have introduced the below stated concepts:

1.  The special instruction (MAC) added to instruction set - CPU augmentation

2.  Address registers updated in the parallel - CPU augmentation

3.  Data registers which are loaded from memory in parallel - Memory banks

4.  Instruction fetched in parallel along with the execution of previous instructions -Harvard architecture and Pipelining 

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