Hardware description language:
- The basic idea is a programming language to describe the hardware
- The module begins with module keyword and finishes with the endmodule.
- The internal signals are named with the wire.
- Comments follow //
- The input and output are ports. These are placed at the beginning of module definition.
- Each statement ends with the semicolon, except the endmodule.
- Design entry by using both behavior and structure
- Simulation modelling
- Testing
- This is a standard language
- Register – It retains the last value assigned to it. Used to represent the storage elements.
- „wire? equivalent; when there are multiple present for drivers driving them, the outputs of the drivers are shorted together.
- Arithmetic operators - *, /, +, -, %
- Logical operators - ! logical negation && logical AND | | logical OR
- Relational operators >, <, >=, <=, ==, !=
- Bitwise operators ~, &, |, ^, ~^
- Reduction operators (operate on all bits within the word) &, ~&, |, ~|, ^, ~^
- accepts a single word operand and generates a single bit as output
- Shift operators >>, <<
- Concatenation { }
- Replication { n { } }
- Conditional <condition> ? <expression1> : <expression2>
![1950_hardware discription language.png](https://www.expertsmind.com/CMSImages/1950_hardware%20discription%20language.png)
The Basic Structure
module module_name (list_of_ports);
input/output declarations;
local net declarations;
parallel statements;
endmodule
Simple AND circuit for HDL
module simpleand (f, x, y);
input x, y;
output f;
assign f = x & y;
endmodule
Simple circuit diagram
![2020_hardware discription language1.png](https://www.expertsmind.com/CMSImages/2020_hardware%20discription%20language1.png)
Simple HDL
module smpl_circuit(A,B,C,x,y);
input A,B,C; output x,y; wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule
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