Biasing the FET:
FET can also be biased as an amplifier. By taking the common source drain characteristic of a JFET. For the linear amplification, Q point should be selected somewhere in saturation region. Q point is selected on basis of the AC performance that is gain, noise, power, frequency response, current and voltage ratings.
Gate Bias:
Figure1, shows the circuit of simple gate bias.
Figure 1
The separate VGS supply is taken in use to set up Q point. This is the worst method to select Q point. The reason is that there is significant variation in between the maximum and minimum values of FET parameters for example
IDSS VGS(off)
Minimum 4mA -2V
Maximum 13mA -8V
This shows that the minimum and maximum transductance curves are displaced as shown in the figure 2.
Gate bias applies the fixed voltage to the gate. The fixed voltage results in the Q point which is highly sensitive to the particular JFET used. For example, if VGS= -1V the Q point may vary from Q1 to Q2 depending upon the JFET parameter is use.
At Q1, ID= 0.016 (1 - (1/8))2 = 12.3 mA At Q2, ID= 0.004 (1-(1/2))2 = 1 mA.
The variation in the drain current is very large.
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