Enhancing the CPU architecture

Inside the loop
How would a general utility CPU carry out computations inside the loop?

Suppose that {b} and {x} are stored as arrays in the memory. Suppose that the CPU has pointer registers j and k which can be directly updated and is used to retrieve data from memory, 2 arithmetic registers b and x which can be used as operands of the arithmetic operations, the double length register p to receive accumulator and product a for summing the products. The instruction sequence for 1 pass through the loop on a general utility CPU looks like this: 

Supposing that every line above takes 1 unit of time - call it an "instruction time" or "clock cycle" - (multiplication takes several units easily of time but we suppose it is the same as the rest), the sequence takes ten units of time to complete it. We could add a "multiply and add" instruction to the instruction set of CPU (which means that, we augment CPU with the suitable hardware): this would merge the last six lines in the above segment into just three lines, and there would then be seven lines taking seven units of time as which is shown below:

 

The DSP can perform a MAC operation in the single unit of time. Several use this feature as the description of a DSP. It is describe below that how it is accomplished. Update the pointers at the same time as they are independent. We add 2 address updating units to the processor hardware. As these two updates can be done in parallel we show them as one line in the sequence, the sequence now taking six units of time:

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