Encoding Techniques

Following are various ways to map data bits to signal elements.

• Non return to zero (NRZ) NRZ codes share the property that voltage level is constant through a bit interval. High level voltage equal to 1bit and Low level voltage equal to 0 bit . sometime problem arises when there is a large sequence of 0s or 1s and the voltage level is maintained at the same value for a long time. This generates a problem on the receiving end because now, the clock synchronization is gone due to lack of any transitions and thus, it is difficult to determine the exact number of 0s or 1s in this sequence.

The two variations are as follows:

1.  NRZ-Level: In NRZ-L encoding, the polarity of the signal will changes only when the incoming signal changes from a 1 to a 0 or from vice-versa. NRZ-L method appears just like the NRZ method, apart from for the first input one data bit. The reason is NRZ does not consider the first data bit to be a polarity change, where in case of NRZ-L does.

2.  NRZ-Inverted: Transition at the beginning of bit interval = bit 1 and No Transition at beginning of bit interval = bit 0 or vice versa. This technique is called as differential encoding.

NRZ-I has an advantage over NRZ-L. let assume a situation when 2 data wires are wrongly connected in each other's place. In NRZ-L all bit sequences will get upturned (B'coz voltage levels get swapped).Where in case of  NAZ-I since bits are recognized by transition the bits will be correctly interpreted. A huge drawback in NRZ codes is that a string of 0's or 1's will prevent synchronization of transmitter clock with receiver clock and a separate clock line need to be provided.

• Biphase encoding: It has these characteristics:

1.  Modulation rate twice that of NRZ and bandwidth correspondingly greater. (Modulation can be explain as the rate at which signal level is changed).

2.  Because there is predictable transition during each bit time, the receiver can synchronize on that transition that is clock is taken from the signal itself.

3.  Since there can be transition at the beginning as well as in the middle of the bit interval the clock operates at twice the data transfer rate.  

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