Design of Series Voltage Regulator:

Fig. 1 shows basic circuit of the series voltage regulator. The operation of this regulator has been discussed in the previous lecture. It consists of series transistor to control output voltage.

Fig. 1

The circuit can be designed by taking two extreme operating conditions,

1.   V_{S max}, I_{Z max}, I _{load min} / β

2.   V_{S min}, I_{Z min}, I _{load max} / β

We calculate R_s for both the conditions and since R_si is constant, we equate these two expressions as in the Equation E-1.

           (E-1)

A design guideline which set I_Z min = 0.1 I Z max. Then we equate the expressions for Equation (E-1) to obtain,

       (E-2)

Solving for I_Z max, we obtain,

      (E-3)

We estimate load resistance by taking the ratio  of minimum source voltage to maximum load current. Since R _load  is large and in the parallel, it can be ignored. This is the worst case since it represents smallest load and thus the maximum load current.

      (E-4)

Output filter capacitor size can be estimated according to permissible output voltage variation and ripple voltage frequency and can be given by

       (E-5)

Since the voltage gain of the EF amplifier is unity, the output voltage of teh regulated power supply is given as,

V_load=V_Z - V_BE    (E-6)

The percent regulation of power supply is given by

       (E-7)

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