Design of JFET amplifier:
To design JFET amplifier, Q point for the DC bias current can be determined graphically. The DC bias current at Q point should lie in between 30% and 70% of IDSS. This locates Q point in the linear region of characteristic curves.
The relationship in between iD and vGS can be plotted on the dimensionless graph (that is a normalized curve) as shown in the figure.
![976_design of JFET amplifier.png](https://www.expertsmind.com/../CMSImages/976_design of JFET amplifier.png)
Figure1
Vertical axis of this graph is iD / IDSS and horizontal axis is vGS / VP. The slope of curve is represented by gm.
A reasonable method for locating the quiescent point close the center of linear operating region is to select IDQ ≈ IDSS / 2 and VGSQ ≈ 0.3VP. Notice that this is close the midpoint of the curve. Further we select vDS ≈ VDD / 2. This gives a broad range of values for vds which keep the transistor in pinch -off mode.
The transductance at Q-point can be found from slope of the curve of figure 1 and can be given by
![2345_design of JFET amplifier1.png](https://www.expertsmind.com/../CMSImages/2345_design of JFET amplifier1.png)
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