Design of JFET amplifier:

To design JFET amplifier, Q point for the DC bias current can be determined graphically. The DC bias current at Q point should lie in between 30% and 70% of I_DSS. This locates Q point in the linear region of characteristic curves.

The relationship in between i_D and v_GS can be plotted on the dimensionless graph (that is a normalized curve) as shown in the figure.

Figure1

Vertical axis of this graph is i_D  / I_DSS  and horizontal axis is v_GS  / V_P. The slope of curve is represented by g_m.

A reasonable method for locating the quiescent point close the center of linear operating region is to select I_DQ  ≈ I_DSS  / 2 and V_GSQ  ≈ 0.3VP. Notice that this is close the midpoint of the curve. Further we select v_DS  ≈ V_DD  / 2. This gives a broad range of values for vds  which keep the transistor in pinch -off mode.

The transductance at Q-point can be found from slope of the curve of figure 1 and can be given by

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