D Latch
module DLatch(D, Control, Q, notQ);
input D, Control;
output Q, Qnot;
reg Q, Qnot;
always @ (Control or D)
begin
end endmodule
if (Control) Q = D; Qnot = ~Q;
D flip-flop
module DFF(D, clock, Q, Qnot, Reset);
input D, clock, Reset;
output Q, Qnot;
reg Q, Qnot;
always @ (posedge clock or negedge Reset)
if (~Reset) {Q,Qnot} = 2?b01;
else {Q,Qnot} = {D, ~D};
endmodule
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