Multiple instruction and multiple data stream (mimd), Computer Engineering

Assignment Help:

Multiple Instruction and Multiple Data stream (MIMD)

In this association, multiple control units and multiple processing elements are prepared as in MISD. But the discrepancy is that now in this association multiple instruction streams function on multiple data streams . Thus, for handling multiple control units, multiple instruction streams and multiple processing elements are organized in the way of  multiple processing elements are conducting multiple data streams from the Main memory as given  in Figure 7. The processors work on their own given data with their own instructions. Tasks implemented by different processors can start or finish at dissimilar times. They are not lock-stepped, as in SIMD computers, although run asynchronously. This classification actually distinguished the parallel computer. That means in the actual sense MIMD organisation is supposed to be a Parallel computer. All multiprocessor systems drop under this classification. Examples include; Burroughs D825, Cray X-MP, C.mmp Cray-2, S1, HEP, Pluribus, Univac 1100/80, IBM 370/168 MP, Tandem/16, IBM 3081/3084, BBN Butterfly, C.m*, FPS T/40000, iPSC, Meiko Computing Surface (CS-1),.

This type of computer organisation is indicated as:

                                                                           Is > 1

                                                                           Ds > 1

                          2217_Multiple Instruction and Multiple Data stream (MIMD).png

Of the classifications discussed over, MIMD organization is the most accepted for a parallel computer. In the actual sense, parallel computers implement the instructions in MIMD mode.


Related Discussions:- Multiple instruction and multiple data stream (mimd)

Uniform memory access model (uma), Uniform Memory Access Model (UMA) In...

Uniform Memory Access Model (UMA) In this model, the main memory is uniformly shared by all processors in multiprocessor systems and each processor has equal access time to sha

What is tcas, tCAS is the number of clock cycles required to access a parti...

tCAS is the number of clock cycles required to access a particular column of data in SDRAM. CAS latency is the column address strobe time, sometimes referred to as tCL.

Register transfer micro-operations, Register Transfer Micro-operations ...

Register Transfer Micro-operations These micro-operations as the name proposes transfer information from one register to another. The information doesn't change during these mi

An example of load-store optimization using expression trees, Give LOAD-STO...

Give LOAD-STORE optimization based on expression trees for the expression (A+B)/(C-D). LOAD-STORE optimization based on expression trees for the expression (A+B)/(C-D) is given

Personal computing environment, Reply and discuss the role of the SAS 70 re...

Reply and discuss the role of the SAS 70 report in reviewing internal controls. Provide publicly available examples of SAS 70 reports and explain. Problem Discuss the

Define wide area network, Q. Define Wide Area Network? Wide Area Networ...

Q. Define Wide Area Network? Wide Area Network (WAN): It takes a large geographical area and frequently owned by a state. Data transfer rate is low (few KBPS to 10 MBPS) and er

Weight training calculations - artificial intelligence, Weight Training Cal...

Weight Training Calculations -Artificial intelligence: Because we have more weights in our network than in perceptrons, first we have to introduce the notation: wij to denote t

Perfect induction, Any identity or equality in Boolean algebra, suchas de M...

Any identity or equality in Boolean algebra, suchas de Morgan's Theorem can be proved usingthe method of perfect induction. 1. All combinations of variables are written down.

Eme, state function and path function

state function and path function

What are the different methods used for handling, What are the different me...

What are the different methods used for handling the situation when multiple interrupts occurs? 1) Vectores interrupts 2) Interrupt nesting 3) Simultaneous Requests.

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd